A 0.13-µm implementation of 5 Gb/s and 3-mW folded parallel architecture for AES algorithm

A new architecture for encrypting and decrypting the confidential data using Advanced Encryption Standard algorithm is presented in this article. This structure combines the folded structure with parallel architecture to increase the throughput. The whole architecture achieved high throughput with less power. The proposed architecture is implemented in 0.13-µm Complementary metal–oxide–semiconductor (CMOS) technology. The proposed structure is...